@article{oai:chuo-u.repo.nii.ac.jp:00001202,
 author = {江川, 遼介 and 杉本, 泰博},
 journal = {中央大学理工学研究所論文集},
 month = {Mar},
 note = {application/pdf, An optimized dummy-fill placement scheme for an on-chip spiral inductor has been proposed. The influence of the dummy-fill size, magnetic strength and magnetic distribution in the vicinity of inductor wires, and the additional stray capacitance between the inductor wires and the silicon substrate on Q-factor (Quality factor) frequency characteristics has been clarified. The proposed layout pattern of the on-chip spiral inductor has regulated the placement of dummy fills. The forbidden area for dummy-fill placement ranges from 10 μm on the outside to 15 μm on the inside of the inductor wires. There are no dummy fills even underneath the inductor wires. The test chip was fabricated by using a 0.18-μm CMOS process with five metal layers. Experimental results show that the proposed scheme involves no degradation of the peak Q-value or the self-resonant frequency compared with an on-chip inductor without dummy fills., 【査読有】},
 pages = {21--29},
 title = {磁界の分布を考慮してダミーフィルを最適に配置したオンチップ・スパイラルインダクタの設計手法},
 volume = {16},
 year = {2011},
 yomi = {エガワ, リョウスケ and スギモト, ヤスヒロ}
}